As fabrication methods have improved and smaller geometry technologies, such as 90-nanometer design, have been developed, the area of silicon required to produce a memory device having a given data storage capacity has continued to decrease. Generally, these technological advances have led to a greater number of memory devices per silicon wafer, and consequently, a lower cost per memory device. Meanwhile, the overall storage capacity of memory devices has been continuously increasing. Unfortunately, this trend has resulted in significantly increasing the complexity involved in the testing of some memory devices. In particular, it has become increasingly challenging to rapidly and cost-effectively identify manufacturing defects in volatile memory devices, such as CMOS SRAM devices (i.e., complimentary metal oxide semiconductor, static random access memory devices).
One type of CMOS SRAM device that is particularly challenging to accurately and effectively test is a multi-port memory device having an array of multi-port memory cells. FIG. 1 illustrates a typical (prior art) multi-port memory cell 10 that is commonly used in multi-port memory devices. Similar to a single-port memory cell, the multi-port memory cell 10 shown in FIG. 1 includes a storage element comprised of two N-channel field effect transistors (FETs) (e.g., T1 and T2) interconnected with two cross-coupled P-channel transistors (e.g., T3 and T4). However, in contrast to a single-port memory cell, the multi-port memory cell 10 is connected to two word-lines and two pairs of bit-lines—one word-line and one pair of bit-lines per read/write port. Accordingly, the storage element of the multi-port memory cell can be independently and simultaneously accessed from each port during a single clock cycle.
Because the storage element of the multi-port memory cell is connected to multiple ports, a multi-port memory cell may be subject to certain states and stress conditions that are difficult to emulate in a testing mode. For example, one particular stress condition that a multi-port memory cell may encounter during normal operation is when both word-lines (e.g., WORD-LINE A and WORD-LINE B in FIG. 1) are asserted, or enabled, at the same time. This may occur, for example, when WORD-LINE A is asserted during a write cycle in which data is being written to the memory cell via PORT A, while WORD-LINE B is being asserted in connection with a read operation to read data from the memory cell via PORT B. It is during these stress conditions that the memory cell is most likely to fail, if the memory cell or the circuit of which the memory cell is a part, has a manufacturing defect.
Traditional testing logic generally tests each memory cell by simply performing a write operation to write a logical data value to the memory cell, followed by a read operation. If the logical data value read from the memory cell matches the logical data value written, then the memory cell, and the circuit of which the memory cell is a part, are assumed not to be defective. During both the read and write operation, the port that is not in use is disabled. For example, the word-line associated with the port that is not in use is kept at a low voltage state, thereby isolating the bit-lines connected to that particular word-line from the data storage element. Consequently, traditional approaches to testing multi-port memory devices fail to test the memory cells in the stressed conditions that the memory cells may encounter during normal operation.
Another problem with traditional multi-port memory testing methods is that often the testing logic used to test the individual memory cells of the array does not operate at the clock frequency at which the device will operate under normal conditions. For example, one common technique used for memory testing is to implement testing logic, sometimes referred to as built-in self-test and repair (BISTR) logic that is physically remote from the memory core (e.g., the array of dual port memory cells). The BISTR logic may generate control and testing signals including data and address signals for testing one or more memory devices. If multiple memory devices are connected to the BISTR, the control and test signals may be heavily loaded, thereby affecting the maximum frequency at which the memory device can be clocked. Moreover, because the BISTR logic is often implemented to be physically separated from the memory core, the testing and control signals may experience a propagation delay in reaching the memory core. Furthermore, it may take more than one clock cycle to generate and set-up the control and testing signals. Consequently, errors that may occur when the memory device is operated at its normal operating frequency may not be detected if the memory device is tested at a frequency other than the normal operating frequency.